On Optimum Switch Box Designs for 2-D FPGAs

Because of their fast turn around time and economic

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Unformatted text preview: sources. Because of their fast turn-around time and economic manufacturing cost for low volume designs, FPGAs have been used in a great amount of digital equipments. FPGA technologies are commonly classified into three major categories: (1) Look-Up-Table (LUT), SRAM based (2) multiplexer, channel organized and anti-fused, and (3) PLD, EPROM based. In this paper, we will study the optimum routing structure problems for the popular LUT and SRAM based two-dimensional (2-D) FPGAs. The architecture of an industrial product of this type is described in [1, 2, 4, 6]. The importance of routing resource issues in FPGAs is never over-emphasized. In commercial FPGA products, the routing resource consumes most of the chip area, and is responsible to most FPGA architecture is shown in of the circuit delay. A typical Fig. 1. The functional blocks (or logic cells) are marked by L, which are separated by vertical and horizontal channels. There are (called channel density) prefabricated parallel wire segments running between each pair of adjacent L-cells in both vertical and horizonta...
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This document was uploaded on 12/26/2013.

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