On Optimum Switch Box Designs for 2-D FPGAs

Figure 1 the architecture of a 2d fpga a 4 e wr

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: . This paper is organized as follow. Section 2 gives definitions and various graph design problems associated with the switch box designs. For completeness, some basis previous results on S-box designs and a decomposition property of global routings will also be mentioned. In Section 3, we provide our new results for optimum or hyper-universal S-boxes. Section 4 shows our experimental results and we give our conclusions in Section 5. £ Figure 1: The architecture of a 2D FPGA. a 4  E ¨ ¨¨  wR ¥ ¨ ¨  u  g D2 1 ¨   "e f  2     ¢ ¥ fp A1 g D2 1 if h 3 e 2 R 4 1 S box e 4 R 3 C a S YI `P C I W P S 2 3 C 1 switches 2 in S box cWI dbP 4 a 3 V 2 I P 1 1 V L £ E ¨  ¨¨   §¢  C I P L I P C switches in C box I P C E S £ E ¨ ¨  ¨   ¢ £ ¨  ¨¨   ¥ ¦¥ H£ T  E E ¥ C  S ¥£ ¥   £  £  C pin of logic cell logic cell   L £ C  L L 1 2 3 4 C ¥¥ L horizontal channel PRELIMINARIES The terminology and symbols of graphs are referred to [3]. Let be a simpl...
View Full Document

Ask a homework question - tutors are online