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EE5518R_II_Chapter6_Aug2011 - Chapter 6 Power Gating Prof...

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10/18/2011 1 Chapter Chapter 6: Power Gating 6: Power Gating Prof Yong LIAN IEEE Fellow Prof. Yong LIAN, IEEE Fellow Provost’s Chair Professor Area Director, Integrated Circuits and Embedded Systems Department of Electrical and Computer Engineering Email: [email protected], Office: E04-05-38 http://www.ece.nus.edu.sg/stfpage/eleliany Editor-in-Chief, IEEE Transactions on Circuits & Systems II Founder, ClearBridge VitalSigns Pte Ltd EE5518R VLSI Digital Circuit Design Part II Outline Power Gating Overview Power Gating Design P G ti A hit t Power Gating Architecture EE5518 R VLSI Digital Circuit Design, Prof. Yong LIAN, [email protected] 2 6 -
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10/18/2011 2 Power Gating Overview •Dynamic and Leakage power profiles •Principles of Power Gating Design •Power Switching – Fine Grain vs. Coarse Grain EE5518 R VLSI Digital Circuit Design, Prof. Yong LIAN, [email protected] 3 6 - •The Challenges of Power Gating •Impact of Power Gating on Classes of Sub-systems Dynamic and Leakage Power Profiles The basic strategy of power gating is to provide two power modes: a low power mode and an active mode. The goal is to switch between these modes at the appropriate time and in the appropriate manner to maximize power savings while minimizing the impact to performance the impact to performance. The power reduction techniques described earlier do not affect the functionality of the design and do not require changes to the RTL. They can be handled fairly transparently from a design and implementation and perspective; power gating is more invasive than clock-gating in that it affects inter-block interface communication and adds significant time delays to safely enter and exit power gated modes. EE5518 R VLSI Digital Circuit Design, Prof. Yong LIAN, [email protected] 4 6 - Shutting down power to a block of logic may be scheduled explicitly by control software as part of device drivers or operating system idle tasks. Alternatively it may be initiated in hardware by timers or system level power management controllers.
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