Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: operties as follows: Cap: output load set to 100fF. Vpulse (from AnalogLib): Voltage 1 = 0, Voltage 2 = VDD, Delay time = 100pS, Rise time = 10pS, Fall time = 10pS, Pulse width = 200pS, Period = 400pS. Solution: For Spectre simulation, we first construct the schematics as the following figure: A “Transient Analysis” is ran with a pulse input source having the pulse-width of 200ps. The simulation result is shown below. We can use the Calculator to measure falling and rising transitions. t PLH 37.94 ps t PHL 27.69 ps FO4 _ Delay (tPLH tPHL ) / 2 32.81 ps 2B Simulate E0→1 as a function of VDD as VDD varies from 1V down to 0.15V (with 50mV increments). To emulate realistic switching cycle in digital logic, set the input switching period to 10×FO4 delay as you scale down VDD. Solution: Let the period of your clock be 40X the FO4 Delay. Electrical Engineering Department Winter 2013 T 40 FO4 _ Delay 1.32ns Find switching energy dissipation. E Vdd i(t )dt 1 250 ps 100 ps i(t )dt 101 4 You can again use the Calculator to find the integration of current. This step can be done while varying Vdd. Following table and figure illustrate how energy dissipation changes with Vdd. Note that near Subthreshold region, you need to allow sufficient amount of...
View Full Document

This note was uploaded on 01/13/2014 for the course EE 115C taught by Professor N/a during the Winter '10 term at UCLA.

Ask a homework question - tutors are online