Hw-04_W13_Sol

For different vdds you have to change the threshold

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Unformatted text preview: shold for calculating propagation delay is 0.3V, not 0.5V. Also, use a longer period for Vpulse in low VDD cases. You may get a wrong number about (or even cannot measure) the propagation delay if the charge/discharge period is so short that Vout cannot approach the threshold voltage (VDD/2). Electrical Engineering Department Winter 2013 Problem 3 – Computing Capacitance Consider the circuit in Figure 2. Calculate the total equivalent capacitance on node X as it charges from 0 to VDD/2. VDD VDD M2 M4 Vin Node X M1 M3 t=0 Figure 2 You can use the following capacitance values in your calculations: Cdb_NMOS = 0.054 fF, Cdb_PMOS = 0.096 fF Cgd_NMOS = 0.136 fF, Cgd_PMOS = 0.255 fF Cg1 = 0.160 fF, Cg2 = 0.300 fF Hint: You might find the annotated slide 24 in lecture 5 of class notes helpful. You should consider Miller effect. Solution: Each inverter contributes to the capacitance at node X First Inverter (M3-M4): ( ) ( Second Inverter (M1-M2): Total equivalent capacitance at node X: )...
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