Hw-04_W13_Sol

Note that near subthreshold region you need to allow

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Unformatted text preview: time for the logic to charge and discharge. Vdd 1 0.95 0.9 0.85 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 0.25 0.2 Isw[A*T] 101 4 9.41 10 15 8.86 10 15 8.257 10 15 7.7 10 15 7.435 10 15 7.165 10 15 6.498 10 15 5.835 10 15 5.172 10 15 4.496 10 15 3.595 10 15 3.25 1015 2.959 10 15 1.446 10 15 6.2 10 17 5.17 10 17 Esw[fJ] 10 8.94 7.974 7 6.16 5.58 5.02 4.224 3.501 2.84 2.25 1.62 1.3 1 0.34 0.0155 0.0103 tplh 37.98ps 40.31ps 43.24ps 46.72ps 50.5ps 56.5ps 63.57ps 73.09ps 86.5ps 106.5ps 138,.9ps 197.3ps 317ps 616.3ps 1.4ns 4.25ns 4.8ns tphl 29.23ps 31.07ps 33.28ps 36.1ps 39.51ps 43.85ps 49.57ps 57.23ps 68ps 84.04ps 110.3ps 158.6ps 270ps 515.8ps 1.2ns 3.185n 9.3ns tp 33.60ps 36ps 38ps 42ps 45ps 50.5ps 57ps 65ps 72ps 95ps 125ps 178ps 293.5ps 566ps 1.3ns 3.7ns 14ns Electrical Engineering Department Winter 2013 Some hints: When running simulation, change all supply voltages (both VDD and VDDLD in Tutorial 2) to 1, 0.95, 0.9, ... 0.15V for delay and energy calculation. But since we have an individual supply voltage for the inverter of interest (VDD in Tutorial 2), you are asked to measure the energy for ONLY one inverter. For different VDDs, you have to change the threshold (VDD/2) as well. If VDD is 0.6V, then the thre...
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This note was uploaded on 01/13/2014 for the course EE 115C taught by Professor N/a during the Winter '10 term at UCLA.

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