211 sample layouts of a cmos nand2 gate and a cmos

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Unformatted text preview: gate and a CMOS NOR2 gate [WAE] 4 Complex CMOS Logic Gate Design The design steps for a more complex CMOS logic, for example AOI22, are the following: First, construct a logic graph of the schematic (Fig.2.12 (a)) using the following steps: a. Identify each transistor with a unique name (A, B, C, and D as in the example). b. Identify each connection to the transistor with a unique name (n1, n2, n3 in the example). Next, construct one Euler path for both the Pull up and Pull down network (Fig.2.12 (b)). a. Euler paths are defined by a path, such that each edge is visited only once. b. A path is defined by the order of each transistor name. If the path traverses transistor A, B, and C, then the path name is {A, B, C}. c. The Euler path of the Pull-up network must be the same as the path of the Pull-down network. d. Euler paths are not necessarily unique. Finally, once the Euler path is found, it is time to draw the stick-diagram (See Fig.2.12(c)). The final step is to draw the layout. Vdd n1 a n1 Vdd d c c b Vdd n2 d q q q n1 Vss c a n3 n3 n2 b a n2 b d c a q b n3 (b) d Vss (c) Vss (a) Fig.2.12 An example of (a) Schematic, (b) Euler Path, and (c) Stick Diagram. 5 2.5 Layout Considerations Device Sizing Fig.2.13 shows a basic transistor which is built from a polysilicon gate, placed over a region of thin silicon dioxide. In the figure, the rectangle represents the edges of the gate material and the other rectangle depicts the edges of the thin oxide area. The oxide layer is referred to as the active layer. The active is where atoms will be implanted to create a transistor. The overlap of the gate and active layers determine the size of the device. Gate 1111 0000 1111 0000 11111111111 00000000000 1111 0000 11111111111 00000000000 Active 1111 0000 11111111111 00000000000 1111 0000 Diffusion 11111111111 00000000000 1111 0000 11111111111 00000000000 1111 0000 11111111111 00000000000 1111 0000 11111111111 00000000000 1111 0000 1111 0000 Fig.2.13 Top layout view of an MOS transistor showing gate area and active diffu...
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This document was uploaded on 01/14/2014.

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