Layout_Examples

Layout_Examples - 2.4 Layout Design Examples The initial...

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1 2.4 Layout Design Examples The initial phase of layout design can be simplified significantly by the use of stick diagrams as shown in Fig.2.8. A stick diagram is a simplified layout form, which contains information related to each of the process steps, but does not contain the actual size of the individual features. Fig.2.8 Examples of stick diagram for inverter The purpose of the stick diagram is to provide the designer a good understanding of the topological constraints, and to quickly test several possibilities for the optimum layout without actually drawing a complete mask diagram. The stick diagram can easily be drawn by hand and is a handy intermediate form between the circuit diagram and the physical layout since it can easily be modified and corrected. It can therefore be used to anticipate and avoid possible problems when laying out the circuit. CMOS INVERTER In Fig.2.9, the mask layout design of a CMOS inverter will be examined step-by-step. Although the circuit consists of one NMOS and one PMOS transistor, there exists a number of different design possibilities even for this very simple circuit. Fig.2.8 shows two such possibilities.
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2 minimum width of Polysilicon minimum contact size minimum separation from contact to polysilicon edge minimum length of active area minimum separation from minimum width of the active area minimum separation from contact to active edge contact to active edge minimum width of the active area minimum contact size Fig.2.9 Design rule constraints which determine the dimensions of a minimum-size transistor [KAL]. First, it is necessary to create the individual transistors according to the design rules (Fig.2.9). Assume that the design goal is to design an inverter with minimum-size transistors. The width of the active area is then determined by the minimum diffusion contact size (which is necessary for source and drain connections) and the minimum separation from diffusion contact to both active area edges. The width of the polysilicon line over the active area (which is the gate of the transistor) is typically taken as the minimum poly width. Then, the overall length of the active area is simply determined by the following sum: (minimum poly width) + 2 x (minimum poly-to - contact spacing) + 2 x (minimum spacing from contact to active area edge). The PMOS transistor must be placed in an n-well region, and the minimum size of the n-well is dictated by the PMOS active area and the minimum n-well overlap over n + . The distance between the NMOS and the PMOS transistor is determined by the minimum separation between the n + active area and the n-well (Fig.2.10 (a)). The polysilicon gates of the NMOS and the PMOS transistors are usually aligned.
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3 minimum separation between n active area and n-well + minimum overlap of n-well over p active area + PMOS NMOS n-well PMOS NMOS GND INPUT VDD OUTPUT n-well n-well VDD contact metal-poly contact (a) (b) Fig.2.10 (a) Placement of one NMOS and one PMOS transistor, and (b) Complete mask layout of the CMOS inverter [KAL].
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Layout_Examples - 2.4 Layout Design Examples The initial...

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