Layout_Examples

Then the overall length of the active area is simply

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Unformatted text preview: overall length of the active area is simply determined by the following sum: (minimum poly width) + 2 x (minimum poly-to - contact spacing) + 2 x (minimum spacing from contact to active area edge). The PMOS transistor must be placed in an n-well region, and the minimum size of the n-well is dictated by the PMOS active area and the minimum n-well overlap over n+. The distance between the NMOS and the PMOS transistor is determined by the minimum separation between the n+ active area and the n-well (Fig.2.10 (a)). The polysilicon gates of the NMOS and the PMOS transistors are usually aligned. 2 n−well n−well VDD contact PMOS n−well PMOS VDD minimum separation between n+ active area and n−well minimum overlap of n−well over p + active area INPUT OUTPUT metal−poly contact NMOS (a) NMOS GND (b) Fig.2.10 (a) Placement of one NMOS and one PMOS transistor, and (b) Complete mask layout of the CMOS inverter [KAL]. The final step in the mask layout is the local interconnections in metal, for the output node and for the VDD and GND contacts (Fig.2.10 (b)). Notice that in order to be biased properly, the nwell region must also have a VDD contact. NAND2 and NOR2 Fig.2.11 shows the sample layouts of a two- input NAND gate and a two-input NOR gate, using single-layer polysilicon and single-layer metal. Here, the p-type diffusion area for the PMOS transistors and the n-type diffusion area for the NMOS transistors are aligned in parallel to allow simple routing of the gate signals with two parallel polysilicon lines running vertically. Also notice that the two mask layouts show a very strong symmetry, due to the fact that the NAND and the NOR gate have a symmetrical circuit topology. 3 VDD 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 VDD 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 VDD A VDD B A B C A B A C C B C 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 GND 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 GND 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 11111 00000 GND 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 GND Fig.2.11 Sample layouts of a CMOS NAND2...
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This document was uploaded on 01/14/2014.

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