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Unformatted text preview: quate power supply bypassing,
layout and mismatch of driver to the driven
As we understand now, turning MOSFET/IGBT
on and off amounts to charging and discharging
large capacitive loads. Suppose we are trying to
charge a capacitive load of 10,000 p from 0 to
15 VDC (assuming we are turning on a
MOSFET) in 25 ns, using a 14 amp ultra high
I = VxC / t Eq. 5.1
-9 = 6 A
I = (15-0)x10000x10 / 25x10
What this equation tells us is that current output
from driver is directly proportional to voltage
swing and/or load capacitance and inversely
proportional to rise time. Actually the charging
current would not be steady, but would peak
around 9.6 Amps, well within the capability of 14
Amp driver. However, driver IC will have to draw
this current from its power supply in just 25 ns.
The best way to guarantee this is by putting a
pair of by-pass capacitors (of at least 50 times
the load capacitance) of complementary
impedance curves in parallel, very close to the
VCC pin of the driver IC. These capacitors
should have the lowest possible ESR
(Equivalent Series Resistance) and ESL
(Equivalent Series Inductance). One good
example of this is high quality surface mount
type monolithic ceramic capacitors. Other
preferred type is SMD Tantalum. One must keep
the capacitor lead lengths to the bare minimum..
A smart way of accomplishing this is to solder the capacitor across the Vcc and ground pin of driver
IC from the bottom (solder side).
Another very crucial point is proper grounding.
Drivers need a very low impedance path for current
return to ground, avoiding loops. The three paths for
returning current to ground are: 1. Between driver IC
and the logic driving it; 2. between the driver IC and
its own power supply; 3. between the driver IC and
the source/emitter of MOSFET/IGBT being driven.
All these paths should be extremely short in length
to reduce inductance and be as wide as possible to
reduce resistance. Also these ground paths should
be kept distinctly separate to avoid re...
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- Winter '08