spring elec 5200 0016200 001 lecture 3 50 some ia 32

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ure 3 50 Some IA-32 Instructions Some PUSH 5-bit opcode, 3-bit register operand 5-b JE | 3-b 4-bit opcode, 4-bit condition, 8-bit jump offset 4-b | 4-b | Spring 2013, Jan 25 . . . 8-b ELEC 5200-001/6200-001 Lecture 3 51 Some IA-32 Instructions Some MOV 6-bit opcode, 8-bit register/mode*, 8-bit offset 6-b |d|w| 8-b | 8-b bit indicates byte or double word operation bit indicates move to or from memory XOR 8-bit opcode, 8-bit reg/mode*, 8-bit base, 8-b index 8-b | 8-b | 8-b | 8-b *8-bit register/mode: See Figure 2.42, page 174. Spring 2013, Jan 25 . . . ELEC 5200-001/6200-001 Lecture 3 52 Some IA-32 Instructions Some ADD 4-bit opcode, 3-bit register, 32-bit immediate 4-b | 3-b |w| TEST 32-b 7-bit opcode, 8-bit reg/mode, 32-bit immediate 7-b Spring 2013, Jan 25 . . . |w| 8-b | ELEC 5200-001/6200-001 Lecture 3 32-b 53 Additional References IA-32, IA-64 (CISC) A. S. Tanenbaum, Structured Computer Organization, Fifth A. Edition, Upper Saddle River, New Jersey: Pearson PrenticeEdition Hall, 2006, Chapter 5. ARM (RISC) D. Seal, ARM Architecture Reference Manual, Second Edition, D. ARM Addison-Wesley Professional, 2000. Addison-Wesley SPARC (Scalable Processor Architecture) PowerPC V. C. Hamacher, Z. G. Vranesic and S. G. Zaky, Computer V. Organization, Fourth Edition, New York: McGraw-Hill, 1996. Organization, Spring 2013, Jan 25 . . . Spring ELEC 5200-001/6200-001 Lecture 3 54 P×T T P Av. execution time per instruction (T) Program size in machine instructions (P) Instruction Complexity Instruction Increasing instruction complexity Spring 2013, Jan 25 . . . ELEC 5200-001/6200-001 Lecture 3 55 URISC: The Other Extreme URISC: Instruction set has a single instruction: label: urisc dest, src1, target Subtract operand 1 from operand 2, replace operand 2 with Subtract the result, and jump to target address if the result is negative. negative. See, B. Parhami, Computer Architecture, from See, Microprocessors to Supercomputers, New York: Oxford, Microprocessors New 2005, pp. 151-153. 2005, Spring 2013, Jan 25 . . . ELEC 5200-001/6200-001 Lecture 3 56 Summary Instruction complexity is only one variable – llower instruction count vs. higher CPI / lower clock ower rate – we will see performance measures later we Design Principles: – simplicity favors regularity – smaller is faster – good design demands compromise – make the common case fast Instruction set architecture – a very important abstraction indeed! 2004 © Morgan Kaufman Publishers Spring 2013, Jan 25 . . . Spring ELEC 5200-001/6200-001 Lecture 3 57...
View Full Document

This document was uploaded on 01/17/2014.

Ask a homework question - tutors are online