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On the ush of a block to memory only dirty words are

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Unformatted text preview: is resident in the cache and it ceases to do so at time- slot 7. The miss that occurs at time- slot 8 is a replacement miss rather than a false- sharing miss because the block was overwritten (replaced) by the block containing vari- able D at time- slot 5. Finally, it is obvious that the miss at time- slot 9 is a true- sharing miss as it brings a new value (B) into cache. b) Only the false- sharing miss that occurs at time- slot 6. (c) Consider the following initial processor cache states and memory contents for a simple bus-based multiprocessor using the MSI (Modified, Shared, Invalid) snooping cache invalidation protocol. Assume that the caches are direct mapped, write-back and contain only two blocks. Each block contains two words (four bytes per word). For simplicity, each word is only shown as two hex characters and there is a valid bit for each word in the cache indicating that the contents of that word is valid (V), dirty (D, i.e., has been written) or not valid (X). Address tags are just the full address; addresses are given in hexadecimal. On a read miss, both words are read into the cache block. On a write miss, assume allocate on write, meaning that both words are first read from memory to fill the block before the cache block is written. On the flush of a block to memory, only dirty words are written. For each of the following parts, each...
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This document was uploaded on 01/18/2014.

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