11 register modules circuit representation 54 8 delay

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Unformatted text preview: Circuit Representation. 5.4-8. DELAY LOCKED LOOP As we know, associated with each global clock input buffer is a fully digital DLL (Delay-Locked Loop) that can eliminate skew between the clock input pad and internal clock-input pins throughout the device. Each DLL can drive two global clock networks. The DLL monitors the input clock and the distributed clock, and automatically adjusts a clock delay element. Additional delay is introduced such that clock edges reach internal flip-flops exactly one clock period after they arrive at the input. This closed-loop system effectively eliminates clock-distribution delay by ensuring that clock edges arriving at internal flip-flops is in synchronism with clock edges arriving at the input pads. Circuit diagram for Delay Locked Loop is illustrated in Figure 5.12 and the design code is also given in Appendix F. 69 Figure 5.12: CLKDLL Module’s Circuit Representation. In addition to eliminating clock-distribution delay, the DLL provides advanced control of multiple clock domains. In addition the DLL also provides four quadrature phases of the source clock, can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16. It has six outputs. The DLL also operates as a clock mirror. By driving the output from a DLL off-chip and then back on again, the DLL can be used to de-skew a board level clock among multiple Spartan- II devices. In order to guarantee that the system clock is operating correctly prior to the FPGA starting up after configuration, the DLL can delay the completion of the configuration process until after it has achieved lock. 5.4-9. BLOCK-RAM The bus implemented in our design known as BusWires. Its width is 8-Bits, providing addresses between 00H-FFH. Since our RISC design have instruction of fixed length i.e. 16-Bits wide, therefore for this design, the memory map consists of the 16-Bit Block-RAM in the address range (00H-FFH). Spartan-II FPGAs incorporate several large block RAM memories. These complement the...
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This note was uploaded on 01/19/2014 for the course ECE 5101 taught by Professor Sass during the Spring '14 term at UNC Charlotte.

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