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detailed description of the display unit see Appendix F. 59 Figure 5.2: Block Diagram of Proc Module. 60 5-4. Processor Internal Components 5.4-1. EXTERNAL CONTROL SIGNALS
As illustrated in Figure 5.2, the following control signals are provided
externally to the processor core for its control and operational functionality.
Resetp is an active hi input, when active; the processor is resetted and various
variables are initialized to their starting default values. Similarly Holdp is an active
low input, when active; only one instruction from memory is allowed to be executed.
The Clockp is an externally generated clock signal that is crucial for the
operation of all processor components. This signal oscillates at a frequency of 50 or
100 MHZ. All operations occur on the rising edge of the clock signal. 5.4-2. CONTROL UNIT
The Control Unit is the brain of the RISC processor. It consists of numerous
outputs and inputs to control the internal functions of the processor as illustrated in
Figure 5.2. This unit has two main inputs; Count is the 4-Bit signal generated by the
machine cycle counter and pcoutput is the 16-Bit instruction fetched from RAM. First
different parts of the 16-bits instruction are decoded. After decoding, the Control Unit
performs the required operation according to the decoded operand I. The Control Unit
has two main outputs; Done is a 1-Bit active high signal, which shows the completion
of an operation and EXE is a 8-Bit signal, which drives the value of data to be
displayed on the external Seven Segment Display.
The Clockp is generated external from the FPGA and driven through an I/O
into the top module Proc. The Proc module includes the Control Unit code and
instantiate all others sub modules named as pcounter, upcount, Ram, alu, Display, dll,
regn and dec2to4. The Spartan-II family FPGA provides four dedicated DLLs for
advanced clock domain control, zero propagation delay and low clock skew between
output clocks signals distributed throughout the device. Therefore,...
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- Spring '14