If something difficult is desired the compiler should

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: mething difficult is desired, the compiler should generate several simple instructions. The more complex instructions consist of a very small amount of the overall execution time of the CPU. Therefore, to avoid complex instructions and optimize the RISC processing power, no complex addressing is allowed and all instructions sets act on the internal register set. These factors make RISC an irresistible choice and most modern processors are built on this form factor. Since RISC designs obtain their speed from simplicity, it is understandable why the corporate technology-world is attracted to such a design [19-21]. 5-3. Processor External Design The Figure 5.2 illustrates the processor’s 8-Bit architecture and the ability to read and write to external memory. The designed processor core consists of Registers, ALU, RAM, Decoders, Counters, Display Unit and Control Unit connected by a Central Bus denoted as BusWires. Control Unit provide the necessary control signals that allow data to be moved or copied over the BusWires as well as for performing an ALU operation on the data. For example, data can be read from an external device into a selected register. There are control signals to allow the contents of any register to be supplied to the temporary register (A) or placed on the BusWires, which in-turn inputs the data to the ALU. Other control signals allow the result from the ALU to be stored back into memory, driven externally to display unit, I/O or driven on the BusWires. Data that is picked from the BusWires can either be clocked into the Register for memory storage or can be latched into the Control Unit as an Instruction. A Display Unit was developed in addition to the core design for hardware debugging 58 purposes. This Display Unit was capable of driving the value of the Data, BusWires or ALU to the Seven Segment Display external to FPGA. This Display Unit has one control signal for its operation known as Done. This Done line works as is an internal switch which selects which value will be shown on seven segment display. For...
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online