Therefore in order to purify the external clock

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Unformatted text preview: in order to purify the external clock signal, it is fed into the DLL module. The output clock signal from DLL module is used as input for rest of the processor circuitry because these 61 dedicated DLLs can be used to implement several circuits which improve and simplify system level design. The maximum number of clock pulses consumed by an instruction is four. The Jump, Move and Load instruction require one machine cycle, while the rest of instruction consume four machine cycles. On every rising edge of the clock, the Control Unit generates the correct signal logic to perform the desired operation. The Resetp and Holdp input are also generated externally and is driven through an I/O into the top module Proc. The Resetp is configured to be an asynchronous reset, meaning the reset must be held down until sufficient clocks have expired to bring the state machine back to the beginning and the Holdp signal is used to execute the code unit step. The circuit design (or RTL Schematics) of the top level module Proc is shown in the following figures. Figures 5.3, 5.4, 5.5 and 5.6 describe all circuitry that will be implemented in the FPGA. Initially, when Resetp signal is high all sub modules of the processor are reset to their default values and the RAM is reloaded with the processor instruction set. The design code for Control Unit is also given in Appendix F. Figure 5.3: Proc module circuit design 1. 62 Figure 5.4: Proc module circuit design 2. 63 Figure 5.5: Proc module circuit design 3. 64 Figure 5.6: Proc module circuit design 4. 5.4-3. ALU The ALU (Arithmetic Logic Unit) is used to perform various bitwise operations. When the ALU performs any operations, it generates the status. Using the flags the Control Unit is able to determine when an overflow, zero, carry, halfoverflow, negative and other conditions have occurred. The ALU perform operations like Additions, Subtractions, Multiplication, AND, NAND, OR, NOR, Not, Shifts and 65 Rotate on the input data from the temporary register A and BusWires. Circuit diagram for AL...
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