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RAM Look-Up Tables (LUTs) that provide shallow memory structures implemented
in CLBs. 70 Block RAM memory blocks are organized in columns. All Spartan-II devices
contain two such columns, one along each vertical edge. These columns extend the
full height of the chip. Each memory block is four CLBs high, and consequently, a
Spartan-II device eight CLBs high will contain two memory blocks per column, and a
total of four blocks as illustrated in Figure 5.13, and the design code is available in
Appendix F. Figure 5.13: Spartan II FPGA Block Diagram. The Spartan-II FPGA XC2S100 provides ten dedicated blocks of on-chip, true
dual-read/write port synchronous RAM, with 4096 memory cells. Each port of the
block RAM memory can be independently configured as a read/write port, a read
port, a write port, and can be configured to a specific data width. The block RAM
memory offers new capabilities allowing the FPGA designer to simplify designs.
Each block RAM cell, as illustrated in Figure 5.14, is a fully synchronous
dual-ported 4096-bit RAM with independent control signals for each port. The data
widths of the two ports can be configured independently, providing built-in bus-width
conversion. 71 Figure 5.14: Block-Ram Module’s Circuit Representation. 72...
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This note was uploaded on 01/19/2014 for the course ECE 5101 taught by Professor Sass during the Spring '14 term at UNC Charlotte.
- Spring '14