Lecture 18

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Unformatted text preview: pera1on in satura1on, Vout cannot fall below Vin by more than one threshold voltage. §༊  The condi1on above ensures opera1on in satura1on. EE105, Fall 2013 Lecture 18 – Slide 3 Prof. Ming C. Wu CS Stage with λ=0 Av = − g m RL Rin = ∞ Rout = RL EE105, Fall 2013 Lecture 18 – Slide 4 Prof. Ming C. Wu 2 CS Stage with λ ≠ 0 Av = − g m (RL || rO ) Rin = ∞ Rout = RL || rO §༊  However, channel length modula1on leads to finite output resistance, ro, which is in parallel with the load resistance, RL Lecture 18 – Slide 5 EE105, Fall 201...
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This note was uploaded on 01/22/2014 for the course EE 105 taught by Professor King-liu during the Fall '07 term at University of California, Berkeley.

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