Ee105 fall 2013 lecture 20 slide 12 prof ming c wu 6

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: nd stage: Common Gate Av = λ2 = 0 Lecture 20 – Slide 10 RD 1 1 + g m 2 g m1 Prof. Ming C. Wu 5 Composite Stage Example 2 §༊  This example shows that by probing different nodes in a circuit, different output signals can be obtained. §༊  Vout1 is a result of M1 acIng as a source follower, whereas Vout2 is a result of M1 acIng as a CS stage with degeneraIon. 1 || rO 2 vout1 gm2 = 1 1 vin + || rO 2 g m1 g m 2 λ1 = 0 vout 2 vin EE105, Fall 2013 1 || rO 3 || rO 4 g m3 =− 1 1 + || rO 2 g m1 g m 2 Lecture 20 – Slide 11 Prof. Ming C. Wu N...
View Full Document

This note was uploaded on 01/22/2014 for the course EE 105 taught by Professor King-liu during the Fall '07 term at University of California, Berkeley.

Ask a homework question - tutors are online