L2 hits take 10 cycles l2 local hit rate is 60

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Unformatted text preview: ugh policy. (c) Writing to a subset of the cache line with a write- back policy. (d) Accessing a very small portion of the disk. (e) None of the above. 27. In the worst case scenario, cache performance can be: (a) Worse than a series of direct access to memory. (b) Still better than a series of direct access to memory. (c) Equivalent to a series of direct access to memory. (d) No relevance to a series of direct access to memory. (e) Equivalent to not having the cache there. 28. The proportional difference in access time from CPU to L1 cache is _________ that from cache to memory. (a) Greater than (b) Less than (c) The same as (d) Undefined in respect to (e) Not enough information 29. The write policy of the cache: (a) Changes the memory address to which the data is written. (b) Causes a memory access to fail. (c) Affects the hit rate of read accesses on the cache. (d) Must be declared by software. (e) None of the above. 30. If instructions without memory- related functions are called: (a) There is no way the caches would get accessed. (b) There is no way the memory will be accessed. (c) There is no way the disk will be accessed. (d) All of the above. (e) None of the above. Section VII: Cache Performance Answer the following questions assuming the following memory/cache organization: 4 GiB Byte- Addressed Memory 256 KiB Direct- Mapped Cache 8 Byte Words 4 Word Blocks 31. Give the Tag : Index : Offset breakdown for the above cache: 8 (a) 16 : 15 : 4 (b) 14 : 13 : 3 (c) 16 : 13 : 3...
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