HW5 - flip-flop input functions and the output functions ,...

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ECE 3550 DIGITAL DESIGN FALL 2006 Homework Assignment #5 Total: 80 pts. Due 11:30am, Friday, October 13, 2006 The logic diagram of a synchronous sequential circuit is given on Page 2. The signals at the outputs of the JK flip-flops change on the falling edge of the signal CLOCK . You should assume that inputs X 1 and X 2 will change on the rising edge of CLOCK. Furthermore, for drawing a timing diagram for the circuit you may assume that the flip- flops and gates exhibit no propagation delays. However, each flip-flop may perform just one state transition at each clock. Tasks 1. Give the
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Unformatted text preview: flip-flop input functions and the output functions , respectively. (6 pts.) 2. Give the combined circuit excitation and output table . (30 pts.) 3. Give the assigned state table . (16 pts.) 4. Draw a state transition diagram for the circuit. (4 pts.) 5. Complete the timing diagram for CLOCK pulses 1-8. Prior to the rising edge of CLOCK pulse #1 the state of the circuit is as follows: y 1 y 2 =01, X 1 X 2 =10, and Z 1 Z 2 =11. The X 1 X 2 input string ( starting on the rising edge of CLOCK pulse #1 ) is 11, 00, 10, 10, 00, 00, 11, and 01. (24 pts.)...
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This homework help was uploaded on 04/07/2008 for the course ECE 3550 taught by Professor Grantner during the Fall '06 term at Western Michigan.

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