Lecture 4_0916

3 for 65 nm 4 nonideal transistor theory cmos cmos

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Unformatted text preview: er law model – Ids VDD – 1 < < 2 determined empirically ( 1.3 for 65 nm) 4: Nonideal Transistor Theory CMOS CMOS VLSI Design 4th Ed. 10 -Power Model 4: Nonideal Transistor Theory CMOS CMOS VLSI Design 4th Ed. 11 Channel Length Modulation Reverse-biased p-n junctions form a depletion region – Region between n and p with no carriers – Width of depletion Ld region grows with reverse bias – Leff = L – Ld Shorter Leff gives more current – Ids increases with Vds – Even in saturation 4: Nonideal Transistor Theory CMOS CMOS VLSI Design 4th Ed. 12 Chan Length Mod I-V = channel length modulation coefficient – not feature size – Empirically fit to I-V characteristics 4: Nonideal Transistor Theory CMOS CMOS VLSI Design 4th Ed. 13 Threshold Voltage Effects Vt is Vgs for which the channel starts to invert Ideal models assumed Vt is constant Really depends (weakly) on almost everything else: – Body voltage: Body Effect – Drain voltage: Drain-Induced Barrier Lowering – Channel len...
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This note was uploaded on 01/22/2014 for the course ECE 261 taught by Professor Morizio,j during the Winter '08 term at Duke.

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