L12-cyclecpu - Datapath Summary The datapath based on data...

Info icon This preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
L12 CPU Design : Designing a Single-Cycle CPU (1) Fall 2007 Datapath Summary The datapath based on data transfers required to perform instructions A controller causes the right transfers to happen PC instruction memory +4 rt rs rd registers ALU Data memory imm Controller opcode, funct
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
L12 CPU Design : Designing a Single-Cycle CPU (2) Fall 2007 How to Design a Processor: step-by- step 1. Analyze instruction set architecture (ISA) datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic (hard part!)
Image of page 2
L12 CPU Design : Designing a Single-Cycle CPU (3) Fall 2007 Review: The MIPS Instruction Formats All MIPS instructions are 32 bits long. 3 formats: R-type I-type J-type The different fields are: op : operation (“opcode”) of the instruction rs, rt, rd : the source and destination register specifiers shamt : shift amount funct : selects the variant of the operation in the “op” field address / immediate : address offset or immediate value target address : target address of jump instruction op target address 0 26 31 6 bits 26 bits op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt address/immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
L12 CPU Design : Designing a Single-Cycle CPU (4) Fall 2007 Step 1a: The MIPS-lite Subset for today ADDU and SUBU addu rd,rs,rt subu rd,rs,rt OR Immediate: ori rt,rs,imm16 LOAD and STORE Word lw rt,rs,imm16 sw rt,rs,imm16 BRANCH: beq rs,rt,imm16 op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits
Image of page 4
L12 CPU Design : Designing a Single-Cycle CPU (5) Fall 2007 Register Transfer Language RTL gives the meaning of the instructions All start by fetching the instruction {op , rs , rt , rd , shamt , funct} MEM[ PC ] {op , rs , rt , Imm16} MEM[ PC ] inst Register Transfers ADDU R[rd] R[rs] + R[rt]; PC PC + 4 SUBU R[rd] R[rs] – R[rt]; PC PC + 4 ORI R[rt] R[rs] | zero_ext(Imm16); PC PC + 4 LOAD R[rt] MEM[ R[rs] + sign_ext(Imm16)]; PC PC + 4 STORE MEM[ R[rs] + sign_ext(Imm16) ] R[rt]; PC PC + 4 BEQ if ( R[rs] == R[rt] ) then PC PC + 4 + (sign_ext(Imm16) || 00) else PC PC + 4
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
L12 CPU Design : Designing a Single-Cycle CPU (6) Fall 2007 Step 1: Requirements of the Instruction Set Memory (MEM) instructions & data (will use one for each) Registers (R: 32 x 32) read RS read RT Write RT or RD PC Extender (sign/zero extend)
Image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern