L14_cpu_multicycle - Whats wrong with our CPI=1 processor...

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Fall 2007 What’s wrong with our CPI=1 processor? Long Cycle Time All instructions take as much time as the slowest Real memory slower than idealized memory Duplicate Resources PC Inst Memory mux ALU Data Mem mux PC Reg File Inst Memory mux ALU mux PC Inst Memory mux ALU Data Mem PC Inst Memory cmp mux Reg File Reg File Reg File Arithmetic & Logical Load Store Branch Critical Path setup setup
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Fall 2007 We will be reusing functional units ALU used to compute address and to increment PC Memory used for instruction and data Our control signals will not be determined directly by instruction e.g., what should the ALU do for a “subtract” instruction? We’ll use a finite state machine for control Multicycle Approach
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Fall 2007 Break up the instructions into steps, each step takes a cycle balance the amount of work to be done restrict each cycle to use only one major functional unit At the end of a cycle store values for use in later cycles (easiest thing to do) introduce additional “internal” registers Multicycle Approach Read register 1 Read register 2 Write register Write data Registers ALU Zero Read data 1 Read data 2 Sign extend 16 32 Instruction [25–21] Instruction [20–16] Instruction [15–0] ALU result M u x M u x Shift left 2 Instruction register PC 0 1 M u x 0 1 M u x 0 1 M u x 0 1 A B 0 1 2 3 ALUOut Instruction [15–0] Memory data register Address Write data Memory MemData 4 Instruction [15–11]
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Fall 2007 Instructions from ISA perspective Consider each instruction from perspective of ISA. Example: The add instruction changes a register. Register specified by bits 15:11 of instruction. Instruction specified by the PC. New value is the sum (“op”) of two registers. Registers specified by bits 25:21 and 20:16 of the instruction Reg[Memory[PC][15:11]] <= Reg[Memory[PC][25:21]] op Reg[Memory[PC] [20:16]] In order to accomplish this we must break up the instruction.
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