L13-cpu-control - Rs nPC_sel Rd Rt RegWr Adder 00 Rt Rd...

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Single-Cycle CPU Control (1) Fall 2008 Putting it All Together:A Single Cycle Datapath imm16 32 ALUctr clk busW RegWr 32 32 busA 32 busB 5 5 Rw Ra Rb RegFile Rs Rt Rt Rd RegDst E x t e n d e r 32 16 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr Equal Instruction<31:0> < 2 1 : 2 5 > < 1 6 : 2 0 > < 1 1 : 1 5 > < 0 : 1 5 > Imm16 Rd Rt Rs clk P C 00 4 nPC_sel P C E x t Adr Inst Memory A d d e r A d d e r M u x 0 1 0 1 = A L U 0 1 WrEn Adr Data Memory 5
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Single-Cycle CPU Control (2) Fall 2008 Review: A Single Cycle Datapath 32 ALUctr clk busW RegWr 32 32 busA 32 busB 5 5 Rw Ra Rb RegFile Rs Rt Rt Rd RegDst E x t e n d e r 32 16 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr zero 0 1 0 1 = A L U 0 1 WrEn Adr Data Memory 5 Instruction<31:0> < 2 1 : 2 5 > < 1 6 : 2 0 > < 1 1 : 1 5 > < 0 : 1 5 > Imm16 Rd Rt Rs nPC_sel instr fetch unit clk We have everything except control signals
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Single-Cycle CPU Control (3) Fall 2008 An Abstract View of the Implementation Data Out clk 5 Rw Ra Rb Register File Rd Data In Data Addr Ideal Data Memory Instruction Instruction Address Ideal Instruction Memory PC 5 Rs 5 Rt 32 32 32 32 A B Next Address Control Datapath Control Signals Conditions clk clk A L U
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Single-Cycle CPU Control (4) Fall 2008 Recap: Meaning of the Control Signals nPC_sel : “+4” 0 PC <– PC + 4 “br” 1 PC <– PC + 4 + {SignExt(Im16) , 00 } Later in lecture: higher-level connection between mux and branch condition imm16 clk P C 00 4 nPC_sel P C E x t A d d e r A d d e r M u x Inst Address 0 1
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Single-Cycle CPU Control (5) Fall 2008 Recap: Meaning of the Control Signals ExtOp: “zero”, “sign” ALUsrc: 0 regB; 1 immed ALUctr: ADD ”, “ SUB ”, “ OR ° MemWr: 1 write memory ° MemtoReg: 0 ALU; 1 Mem ° RegDst: 0 “rt”; 1 “rd” ° RegWr: 1 write register 32 ALUctr clk busW RegWr 32 32 busA 32 busB 5 5 Rw Ra Rb RegFile Rs Rt Rt Rd RegDst E x t e n d e r 32 16 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr 0 1 0 1 A L U 0 1 WrEn Adr Data Memory 5
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Single-Cycle CPU Control (6) Fall 2008 RTL: The Add Instruction add rd, rs, rt MEM[PC] Fetch the instruction from memory R[rd] = R[rs] + R[rt] The actual operation PC = PC + 4 Calculate the next instruction’s address op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits
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Single-Cycle CPU Control (7) Fall 2008 Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction = MEM[PC] same for all instructions imm16 clk P C 00 4 nPC_sel P C E x t A d d e r A d d e r M u x Inst Address Inst Memory Instruction<31:0>
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Single-Cycle CPU Control (8) Fall 2008 Instruction Fetch Unit at the End of Add PC = PC + 4 This is the same for all instructions except: Branch and Jump imm16 clk P C 00 4 nPC_sel=+4 P C E x t A d d e r A d d e r M u x Inst Address Inst Memory
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Single-Cycle CPU Control (9) Fall 2008 The Single Cycle Datapath during Add R[rd] = R[rs] + R[rt] op rs rt rd shamt funct 0 6 11 16 21 26 31 32 ALUctr= ADD clk busW RegWr=1 32 32 busA 32 busB 5 5 Rw Ra Rb RegFile Rs Rt Rt Rd RegDst=1 E x t e n d e r 32 16 imm16 ALUSrc=0 ExtOp=x MemtoReg=0 clk Data In 32 MemWr=0 zero 0 1 0 1 = A L U 0
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