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st Te a)  Fill in the main routine below to configure mydev for an interrupt on ready to
read, and to enable the interrupt so that it can occur as soon as the processor reaches label
PSIT. Assume that the code after PSIT does not change the interrupt configuration of the
processor or the device, but of course, it can read and write any registers and memory as
allowed by the programming conventions for NIOS II.
Downloader ID: 11691 Test ID: 3251 Downloader ID: 11691 Do wn
lo ad .section .text
.global main er
ID : 11 69 1 main: er ID: 11691 # your code goes here
movi r8, 0x1000
# enable IRQ12
movi r8, 0x10 # enable read interrupts on the device
movi r8, 0x1
# enable interrupts on the CPU
: wn st Do Te lo ad er ID : 11 69 1 Download 32
51 Downlo 11691
ader ID: 69
1 st ID
: 32 51 Test ID: 3251 11
69 1 Do ad
e r ID : 11 Downloader ID: 11691
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: Do wn 1 69 11 Test ID: 3251 69 : ad lo Do # Unknown code follows at this point
51 PSIT: ID : 32 …. Tes nl
oa ID: 11691 t ID: 1 325 Do
w Downloader de r ID : 11 Te 69 1 st -3 if device interrupts are not enabled
-2 if the STW is there but either does not write to the right address or the r
-3 if IRQ12 is not enabled (ctl3)
-1 if the write for ctl3 is there but the value is not right
-3 if interrupts are not enabled on the CPU (ctl0)
-1 if the write to ctl0 is there but the value is incorrect
Downloader ID: 11691 0 if no attempt was made
er ID: 1169 1 load Down Do
1 Test ID: 3251 51 : ID
st Te Oxdia @ http://www.oxdia.com
This test is copyrighted by the uploader and/or course instructor.
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Test ID: 3251 Unauthorized reproduction/distribution is strictly prohibited.
Solution (if any) is NOT audited, so use at your discretion. 32 wn er ID 11 1 1
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1 b)  Assuming your answer in (a), the interrupt handler below will be invoked
whenever a value is ready to read from mydev. Fill in the interrupt handler below to
implement an “echo”, that is, whenever you receive a character, read it and then write it
back as output. Write the instructions for each part of the handler under the associated
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This document was uploaded on 01/28/2014.
- Winter '14