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Unformatted text preview: so that they appear in numerical order with the register with the lower
number appearing on the top of the stack. If a section is empty (there is no need
for instructions in that section) then just write the comment “#empty”.
11 : ID er ad lo wn Do 1 69 ID ad : 11 er lo wn 52 Do ADDI SP, SP, __-12__
# PROLOGUE – REGISTER SAVING STORES GO HERE
STW ra_, 8(SP) st ID
: 32 FOO: 11 69
1 STW r16_, 4(SP)
t ID: Tes Do wn lo ad
e r ID : # MAIN FUNCTION BODY
ADD R16, R5, R6
ADD R16, R16, R4
# PRE-CALL, REGISTER SAVING STORES GO HERE
: STW r7_, 0(SP)
52 Down ID st Te : 32 52 CALL BOO
# POST-CALL, REGISTER RESTORING LOADS GO HERE
LDW r7_, 0_(SP)
ADD R2, R7, R2
ADD R16, R16, R2
ADD R16, R16, R2
LDW R2, 0(R16)
# EPILOGUE – REGISTER RESTORING LOADS GO HERE
LDW r16_, _4_(SP)
load 1169 1 ad
69 1 st Te : ID r 52 32 : ID
: ID Do
lo 11 Te 69 1 st er ID: 2 325 t ID: nl
oa de Tes Do
w LDW ra_, _8_(SP)
ADDI SP, SP, _12__
RET 691 -2 for any register not saved
-2 for any register not restored at the right place or not restored at all
-2 for incorrect indexing in the stack
-1 for any incorrect stack adjustment (e.g., if +6 appears in the prologue and -6 in the
epilogue subtract -2)
-1 for mistakes that cause wrong execution
OK if ADDI was changed to SUBI
Ignore the actual ordering of registers in the stack as long as it is consistent.
Tes t ID: 325 2 3252
Test ID: Oxdia @ http://www.oxdia.com
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Solution (if any) is NOT audited, so use at your discretion.
3252 load er ID: 1
t ID : 32
52 Page 10 of 11 Last Name (in case pages get detached):__________________
: 32 52 ID
Te st Tes t ID:
325 8.  Interrupt Handling: There are several steps to properly initializing an 2 Downloader ID: 11691 Test ID: 3252 interrupt. Furthermore, when an interrupt happens several events occur. Put the
following actions/events in proper order for both initialization and events that follow
the occurrence of the interrupt (but before the interrupt handler starts executing).
Simply give the ordered list of letters for each. Note that there are multiple correct
orders, and that some items should be left out of the solution (i.e., there are decoys).
Assume that PC contains the address of the instruction that was in the middle of
executing when the interrupt was taken. Test ID:
3252 Test ID: 3252 A) the value of PC+4 is written to the ea register
B) the value of PC is written to the ea register
C) the ea register is copied to the PC
D) ctl0 is copied to ctl1
E) ctl1 is copied to ctl0
F) the current instruction is aborted
G) the current instruction completes execution
H) interrupts are enabled at the device
I) the PIE bit in ctl0 is set to 0
J) the PIE bit in ctl0 is set to 1
K) the appropriate bit of ctl3 (ienable) is set
L) the PC is set to 0x1000020
M) ctl4 (ipending)...
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This document was uploaded on 01/28/2014.
- Winter '14