LFIB_Notes

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Unformatted text preview: 00 0.000 61 3 9 0.188 0.562 0 0 0.000 0.000 62 8 0 0.500 0.000 1 1 0.062 0.062 63 1 3 0.062 0.188 0 2 0.000 0.125 64 3 13 0.188 0.812 0 0 0.000 0.000 65 12 12 0.750 0.750 0 0 0.000 0.000 66 1 3 0.062 0.188 1 5 0.062 0.312 67 5 3 0.312 0.188 0 0 0.000 0.000 68 8 4 0.500 0.250 0 0 0.000 0.000 69 9 1 0.562 0.062 2 4 0.125 0.250 70 7 11 0.438 0.688 0 2 0.000 0.125 71 6 6 0.375 0.375 0 0 0.000 0.000 72 4 12 0.250 0.750 1 1 0.062 0.062 73 2 6 0.125 0.375 1 7 0.062 0.438 74 8 0 0.500 0.000 0 0 0.000 0.000 75 4 0 0.250 0.000 0 0 0.000 0.000 76 10 4 0.625 0.250 3 9 0.188 0.562 77 12 14 0.750 0.875 0 2 0.000 0.125 78 14 10 0.875 0.625 0 0 0.000 0.000 79 13 13 0.812 0.812 3 5 0.188 0.312 80 9 1 0.562 0.062 1 9 0.062 0.562 81 14 6 0.875 0.375 0 0 0.000 0.000 82 8 12 0.500 0.750 1 1 0.062 0.062 83 12 10 0.750 0.625 4 0 0.250 0.000 84 4 14 0.250 0.875 0 2 0.000 0.125 85 2 10 0.125 0.625 Remarks X(9) X(15) X(8) X(14) X(7) X(13) X(6) X(12) X(5) X(11) X(4) X(10) X(3) X(9) X(2) X(8) X(1) X(7) X(0) 37 X(6) vector length (k-1) Figure 12: Vectorized Stepping of LFG(10,7,M) cycles. For all other bit elds, including the next-to-least signi cant, there is no such defect. Several possibilities arise for remedying this situation, including the use of a separate, independent generator for only the least signi cant bit. However, in the interest of simplicity and speed, Pryor et al. have chosen to shift o the least signi cant bit of the generated random number, so that the numbers returned by the generator are in the range 0 231 ; 1] rather than 0 232 ; 1]. The register is initialized and maintained as a 32-bit generator, so that no loss of period length or uniqueness of cycle is incurred. And for 32-bit machines, the returned results still include all positive integers. 38 As mentioned in the beginning of this section, there is at least limited potential for vectorization of a single lagged Fibonacci generator. Figure 12 is an illustration of vectorization applied to our LFG(10 7 M ) generator. As the gure shows, the vector algorithm advances the register ahead by (k ; 1) steps, so that the vector length of most of the operations is (k ; 1). Note that there is a vector copy operation of length (` ; (k ; 1)). Care should be taken that no item of data is destroyed before it is needed. The easiest way to prevent unintentionally writing over needed data is to keep two copies of the Fibonacci register and, for each \vector" advance, use the old copy to construct the new one. None of the data in the old copy will be destroyed until the next vector advance, when it becomes the new copy. If vectorization of the Fibonacci generator is important | and it could be, if random number generation consumes a large fraction of the execution time | then clearly a long vector length is better than a short one. Processing with a vector length of 6, as our example has, would not yield much improvement over the scalar method. For vectorization to provide meaningful improvement over scalar processing, the vector operations should be long enough to make good use of the machine hardware. For example, on Cray machines where the vector registers are 64 words long (128 on the new models), this usually means vector lengths of tens of elements. For these machines, the generators LFG(71 65 M ) and LFG(159 128 M ) would be good choices, with respective vector lengths of 64 and 127. In Figure 13 we list a sample Fortran code for initializing and generating random numbers from the generator LFG(17 5 32). Note that the register is maintained as a set of 32-bit numbers, but that the number returned to the user has only 31 bits. The initialization of the register is accomplished using the Park and Miller LGC described in Park and Miller, 1988]. The seed, \iseed0," supplied by the user may be any integer greater than or equal to zero and less than or equal to 231 ; 2 = 2,147,483,646. The register is initialized in canonical form, so each value of iseed0 results in a distinct cycle of random numbers. Since the function irnd175() was written to work on 64-bit machines, as well as 32-bit machines, the mask operations were included to add clarity to the code. In many situations, the 32-bit mask operation could be eliminated, since the hardware would simply ignore any over ow. The 31-bit mask could also be eliminated on any systems that zero- ll on right shift operations. If the system performs a \sign extension" type of ll, then the 31-bit mask would be required. Exercise 10 - to explore LFGs visually Use the code ranlf.f to generate random numbers. Modify the code to print out pairs of random numbers on 0,1) and display them as points as Rn+1 vs. Rn for 4,095 points (4,096 random numbers). (a) Using ` = 17 (n varies from 0 to 16), and k = 12, select a subtractive generator. Use an initial seed of 37 to generate the initial state. Compare the display to those of Figures 6a-f in Section 4 which were generated using LCG generators. (b) Select di erent values for k, but keep ` xed at 17. Use the parameters as in...
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This document was uploaded on 01/28/2014.

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