Write interface cell array 42 lets build some more

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Unformatted text preview: chips – Transistors – Wires to connect transistors 33 34 35 36 Wires • Four levels of wires shown here • Designers specify each layer and connections between layers Source: IBM Chip Wires • Modern chips have up to 8 layers of wires Source: IBM 37 Chip Wires Source: IBM Transistor Layout • Drawing a transistor is this easy DRAIN PMOS transistor SOURCE GATE GATE NMOS transistor DRAIN SOURCE Source: Mike Lai 38 AND Gate Layout POWER SUPPLY • Here is an AND gate (with an inverted output, which is called a NAND) INPUT1 OUTPUT INPUT2 GROUND Source: Mike Lai OR Gate Layout • Here is an OR gate (with an inverted output, which is called a NOR) POWER SUPPLY INPUT1 INPUT2 OUTPUT GROUND Source: Mike Lai 39 Full Adder Layout • Here is a Full Adder Source: Mike Lai 16-bit Adder Layout • Here is a complete 16‐bit adder (it adds two numbers where each input can range from –32,000 to +32,000) • This adder contains 16 full adders (essentially) plus additional circuits for fast addition Source: Mike Lai 40 16-bit Multiplier Layout • Here is a complete 16‐bit x 16‐bit multiplier (each input can range from –32,000 to +32,000) Source: Mike Lai Layout: Flip flop • Stores one bit of information clk Vdd data_in Gnd 41 Layout: 6-transistor memory cell Bitline Bitline_ • Two 6‐transistor SRAM cells • Small area is everything Wordline0 Wordline1 Gnd Vdd Layout: 6-transistor cell array Data read and write interface Cell array 42 Let’s Build Some More Complex Things • We’ll use our big building blocks – Memory • Silicon memories – Datapath • Adders/subtracters • Multipliers • Shifters – Controllers • And LOTS of wires to connect things Example #1 An FFT Processor • One of the most widely used digital signal processing tasks • Used in: – – – – Communications Radar Inst...
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This note was uploaded on 01/29/2014 for the course MAT 1 taught by Professor Higgins during the Fall '13 term at UC Davis.

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