This preview shows page 1. Sign up to view the full content.
Unformatted text preview: Cell Design (Transistor sizing)
§12.2 SRAM cell Design
- Find sizes of all MOSFETs
- SRAM Cell is symmetrical so only need to find 3 sizes
- Since L = 2!, our results will be widths W1,2, W3,4 and W5,6 Design requirements:
State of SRAM should not change due to a read operation
3) Read Speed
READ operation should be performed within specified time
2) Write ability
We must be able to alter the state of the SRAM through the bitlines
Parameters used for sizing example:
V_DD = 2.5V
V_tn = |V_tp| = 0.5V
µ_n = 0.2mA/V^2
µ_p = 0.1mA/V^2
C_BL = C_!BL = 1pF Capacitance of the bitlines See detailed derivation and assumption in following pages Final results:
With our design assumptions and given parameters,
we obtained 3 inequalities
1) Read stability:
2) Read speed:
3) Write ability: W1,2
W5,6 >= 1.3 W3,4
>= 2.2 7!/2! 7!/2! <= 1.56 W3,4 Thus we choose
(W/L)3,4 = 2.5 = 5!/2!
W5,6 >= 1.3(5!)=6.5! <= 1.56W3,4=7.8! -> W3,4 = 5!
-> W1,2 = 7!
-> W5,6 = 7! 5!/2!
5!/2! Read Stability
SRAM Cell Design
Word line is LOW Word line is HIGH 1)...
View Full Document
- Winter '09