Lecture29_30_12.2SRAM_cell_sizing_posted(1)

# 5ma but id4 0225wl4 thus set 0225wl4 05ma wl4

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Unformatted text preview: to produce a differential voltage of ∆v= 100mV within a read time of ∆t=200ps I_D4 &gt;= C_BL ∆v/∆t &gt;= (1pF)(100mV)/(200ps) &gt;= 0.5mA But I_D4 = 0.225(W/L)4 Thus set 0.225(W/L)4 &gt;= 0.5mA (W/L)4 &gt;= 2.2 (e.g. 5!/2!) Eq. 1 Write Ability 3) Write ability: - Pass transistors must be strong enough to overcome back-to-back inverters and change the state of the latch Consider changing Q from ‘0’ to ‘1’: - Not possible to write a ‘1’ into SRAM cell because M2 and M4 are sized to keep V_Q &lt; Vtn (Read stability) - Thus we must be able to write a ‘0’ into the opposite side, !BL Initial state (Q=’0’, !Q =’1’ (before WL goes HIGH) Bitline drivers Just after WL is HIGH We ensure WRITE ability by sizing M3 and M5 such that V_!Q is low enough that the latch toggles its state. FINAL STATE (Q=1, !Q=0) Here assume V_Q &lt;= V_tn: I_D5 = 1/2•µ_p•C_ox•(W/L)5•(V_DD - V_tn - |V_tp|)^2 = 1/2(0.1)(W/L)5•(2.5-0.5-0.5)^2 = 0.1125(W/L)5 I_D3 = = = = Setting µ_n•C_ox•(W/L)3•[(V_DD-V_tn)•V_Q - 1/2•V_Q^2] (0.2)(W/L)3•[(2)0.5 - 0.5^2/2)] 0.2*7/8•(W/L)3 0.175(W/L)3 I_D5 = I_D3 0.1125(W/L)5 = 0.175(W/L)3 (W/L)5 = 1.56 (W/L)3 W5 &lt;= 1.56 W3 (setting W5 narrower ensures M3 dominates so V_!Q &lt;=V_tn)...
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## This document was uploaded on 02/03/2014.

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