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Lecture29_30_12.2SRAM_cell_sizing_posted(1)

Lecture29_30_12.2SRAM_cell_sizing_posted(1) - Lecture 29 30...

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Lecture 29 & 30 SRAM Cell Operation and Design Lecture 29 Notes: SRAM cell Operation (Intro) ==================== §12.2.1 SRAM cell 6T (transistor) SRAM cell circuit features of 6T SRAM cell: ========================= - static latch - feedback loop always present - pass transistors M3 & M4 are NMOS only for reduced area - bit lines (BL and !BL) serve as - differential inputs during a WRITE operation - differential outputs during a READ operation WRITE operation ================ 1. bitlines BL and !BL are set to desired value (e.g. BL=0, !BL=1) - wordline raised HIGH to set new SRAM value and then returned to LOW for storage key: - write operation performed by side writing the ‘0’ - NMOS pass transistor on the ‘1’ side does little READ operation ============== - bitlines BL & !BL are first precharged HIGH ( Φ HIGH) - wordline is raised HIGH - again, operation dominated by side of the cell holding the ‘0’ (Q) which slowly discharges BL or !BL - NMOS pass transistor on the ‘1’ side (!Q) remains OFF - sense amplifier (attached to BL and !BL) detects small differential voltage between BL and !BL precharge for next cycle
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