Final Exam Solutions

Stage 2 decode and rename the instructions choose up

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Unformatted text preview: alue, but not $p2 because we actually need the value produced by instruction (1) 3) SUB $p8, $p12, $p0 $t2 gets renamed to $p12 because we are looking for the value produced by instruction (2) 4) LW $p4, 0($p5) 5) ADD $p14, $p0, $p4 See note on instruction (2) (d) Assume an out ­of ­order processor with a 5 ­stage pipeline that works as follows: • Stage 1: Fetch 2 instructions from memory. • Stage 2: Decode and rename the instructions; choose up to 2 ready instructions to issue to the execution units. • Stage 3: (identical to MIPS EX stage, except that 2 instructions can be processed at once) • Stage 4: (identical to MIPS MEM stage, except that 2 instructions can be processed at once. We unrealistically assume a 1 ­cycle memory access time in all cases.) • Stage 5: Write back to the physical register file; update the reorder buffer; “officially” complete up to 2 instructions by removing them...
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This note was uploaded on 02/08/2014 for the course CS 351 taught by Professor Dr.suzannerivoire during the Fall '13 term at Sonoma.

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