Final Review Quiz

For the following mips code 1 lw t1 0t2 2 addi

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Unformatted text preview: (e) This question does not refer to the snippet of code used in Parts (a) ­(d). In MIPS or a higher ­level language, show an example of code motion. 4 Question 3: Exploiting ILP [25 points]. For the following MIPS code: 1) LW $t1, 0($t2) 2) ADDI $t1, $t1, 1 3) SW $t1, 0($t2) 4) ADDI $t2, $t2, 4 5) SUB $t4, $t3, $t2 6) ADDI $t4, $t4, 1 (a) List the dependencies and antidependencies. For each, give the 2 instructions and the register involved, and state whether it is a true dependency or an antidependency. (b) Rename the instructions using physical registers $p0 through $p63. 5 (c) Assume a 5 ­stage pipeline that works as follows: • Stage 1: Fetch 2 instructions from memory. • Stage 2: Decode and rename the instructions; choose up to 2 ready instructions to issue to the execution units. • Stage 3: (identical to MIPS EX stage, except that 2 instructions can be processed at once) • Stage 4: (identical to MIPS MEM stage, except that 2 instructions can be processed at once) • Stage 5: Write back to the physical register file; update the reorder buffer; “officially” complete up to 2 instructions by removing them from the reorder buffer. Assume that an instruction can start Stage 3 in the cycle immediately after its operands are produced. That is, assume that the issue logic can figure out that an instruction’s operands will be ready in time for the next cycle. List the instructions (by number) that will be fetched in Cycle 1: List the instructions (by number) that will be fetched in Cycle 2: List the instructions (by number) that will be decoded and renamed in Cycle 2. Label each instruction either with “READY” or with the phys...
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This note was uploaded on 02/08/2014 for the course CS 351 taught by Professor Dr.suzannerivoire during the Fall '13 term at Sonoma.

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