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Final Review Quiz

If an instructions operands will be ready at the end

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Unformatted text preview: ical register(s) it must wait for before it can execute. Mark instructions that will advance to Stage 3 in the next cycle with a *. List the instructions (by number) that will be fetched in Cycle 3: List the instructions (by number) that will be decoded and renamed in Cycle 3: 6 List the instructions that are currently in the instruction window during Cycle 3. Label each instruction either with “READY” or with the physical register(s) it must wait for before it can execute. If an instruction’s operands will be ready at the end of Cycle 3, mark it as “READY.” Mark instructions that will advance to Stage 3 in the next cycle with a *. List the instructions (by number) that will be decoded and renamed in Cycle 4: List the instruction(s) (by number) whose results will be ready at the end of Cycle 4: List the instructions that are currently in the instruction window during Cycle 4. Label each instruction either with “READY” or with the physical register(s) it must wait for before it can execute. If an instruction’s operands will be ready at the end of Cycle 4, mark it as “READY.” Mark instructions that will advance to Stage 3 in the next cycle with a *. List the instructions that are currently in the instruction window during Cycle 5. Label each instruction either with “READY” or with the physical register(s) it must wait for before it can execute. If an instruction’s operands will be ready at the end of Cycle 5, mark it as “READY.” List the instruction(s) (by number) that will reach the reorder buffer at the end of Cycle 5. Will these instruction(s) be able to officially commit, or will they remain in the reorder buffer? 7 8 Question 4: Cache coherence [20 points]. For this problem, see the state machine on the final page of this test, which is identical to Figure 9.3.4 in your textbook. (a)Fill out the following chart for a two ­processor system e...
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