Appendix-C-m3-ziavras

from a few to hundreds of clock cycles such as in

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Unformatted text preview: y update during instr. execution (VAX: string copying) (VAX: string copying) – Implicitly setting condition codes – Multicycle operations (widely varying execution times for instrs., from a few to hundreds of clock cycles, such as in VAX) » VAX 8800 solution: pipeline microinstruction 8800 solution: pipeline microinstruction execution » Since 1995, all Intel IA-32 microprocessors pipeline microinstructions/microoperations S. Ziavras Extending the MIPS Pipeline for Multicycle Operations Multicycle Operations • Now also assume FP operations • Impractical for FP operations to complete in 1-2 clock for FP operations to complete in clock cycles (because of slow clock or very large # of gates) • Focus on HW resources (throughput and/or cost issues) – FP pipeline with longer operation latencies • Better throughput – Integer and FP operations share same pipeline FP • Reduce HW resources – EX may be used many times to complete a single FP may be used many times to complete single FP operation • Reduce HW resources – Multiple instances of FP units FP • Better throughput for common operations (e.g., +) S. Ziavras Extending the MIPS Pipeline for Multicycle Operations (2) Multicycle Operations (2) – Assume here: 4 FUs (no pipelining inside units) » Integer unit: load, store, integer ALU, branch operations » FP & integer multiplier integer multiplier » FP adder: FP add, subtract, conversion » FP & integer divider S. Ziavras FU: (latency, initiation interval) Integer ALU: (0, 1) Data mem. (integer & FP load): (1, 1) FP+: (3, 1) FP & integer *: (6, 1) FP & integer /: (24, 25) Load lat. 1: res. available lat 1: res available after 1 intervening cycle L...
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