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Ziavras example pipeline timing muld if id m1 m2 m3

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Unformatted text preview: at. 0 for int. ALU: for int ALU: res. available on next clock cycle Latency: how many stages after EX result is produced S. Ziavras Pipelined Version • Multiply & add units are pipelined • Divider unit is not pipelined (24 cycles for result) S. Ziavras Example: Pipeline Timing MUL.D IF ID M1 M2 M3 M4 ADD.D IF ID A1 A2 A3 ID A1 A3 L.D IF ID EX MEM S.D IF ID EX ID EX Input data M5 M6 M7 MEM WB A4 A4 MEM WB WB WB MEM WB Produced data S. Ziavras Assumption: ID Stage Does Hazard Assumption: ID Stage Does Hazard Detection • ID stage carries out 3 checks – Checks for structural hazard » Wait until FU is available: only needed for division » Register write port is available when write port is available when needed – Checks for RAW data hazard – Checks for WAW data hazard S. Ziavras Precise Exceptions • Difficulty because of multicycle FP instructions • Example without dependencies DIV.D F0,F2,F4 ADD.D F10,F10,F8 SUB.D F12,F12,F14 • Problem with out-of-order completion: an instr. issued earlier may complete after an instr. issued later (ADD.D & SUB.D will finish before DIV.D) • If SUB.D causes an FP arithmetic exception after ADD.D has completed but DIV.D hasn’t imprecise exception exception S. Ziavras 4 Techniques to Alleviate Problems of Out Out-Of-Order Completion Completion 1. Ignore problem & settle for imprecise exceptions in 1960s and early 1970s • Used in 1960s and early 1970s • Difficult to employ nowadays (because of virtual memory & IEEE FP) • Some processors use 2 modes of execution processors use modes of execution • Fast mode (possibly imprecise) • Slower mode (precise): mode switch or (p insertion o...
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