Appendix-C-m3-ziavras

Ziavras out of order exceptions however exceptions

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Unformatted text preview: WB MEM: data page fault EX: arithmetic exception • Service MEM & restart MEM restart – EX exception will appear again later S. Ziavras Out-of-order Exceptions • However, exceptions may occur out of order • Earlier example: LD (data page fault). DADD (instr. page fault now) – Instr. page fault will occur before data page fault! page fault will occur before data page fault! – Since we assume precise exceptions, pipeline must handle data page exception before instr. page exception page exception S. Ziavras Out-of-order Exceptions (2) Solution • Hardware posts all exceptions caused by a given posts all exceptions caused by given instr. in an exception status vector for this instr. • If any bit in this vector is set, any control signal that may write value in reg or the memory is turned off may write a value in a reg. or the memory is turned off • Upon reaching WB, exception status vector is checked. If exceptions have been posted, they’re handled in order corresponding to an unpipelined processor procedure, forces in handling of • This procedure, forces in-order handling of exceptions for a set of instrs. • Difficult to implement for FP instrs. S. Ziavras Instruction Set Complications • No MIPS instr. has more than 1 result • MIPS (integer) pipeline writes result in WB • Committed instruction: guaranteed to complete (it has not raised any exception or any exception has has not raised any exception, or any exception has been taken care of and the instruction is ready to write its result) • Because of above in MIPS: exceptions are precise of above in MIPS: exceptions are precise S. Ziavras Instruction Set Complications (2) • Processors exist that change state in middle of instr. execution – Autoincrement addressing modes – Memor...
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This document was uploaded on 02/09/2014.

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