Appendix-C-m3-ziavras

Appendix-C-m3-ziavras

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Unformatted text preview: h delay) branch delay) + 1 Pipeline capable of precise exceptions: instrs. just before faulting instr. are completed and those after it can be restarted from scratch those after it can be restarted from scratch S. Ziavras Floating-Point Exceptions • Faulting FP instr. on some processors writes its result before exception can be handled before exception can be handled • Then, HW should be able to retrieve source operands (even if destination is same as one source) • FP operations may run for many cycles, so some other instruction(s) may have written source operands (FP operations often complete out of order) (FP operations often complete out of order) S. Ziavras Floating-Point Exceptions (2) • To solve the latter problem, many recent processors use 2 modes of operation – Precise exceptions (slower mode; less overlap of FP operations) – Fast/performance (mode not supporting precise not supporting precise exceptions) --------------------------------– Alpha 21064, Power2, MIPS R8000: precise exceptions mode is often more than 10 times slower than fast mode slower than fast mode good only for debugging only for debugging – Processors supporting demand paging or IEEE arithmetic trap handlers must make their exceptions precise (hardware and/or software exceptions precise (hardware and/or software support) S. Ziavras MIPS Exceptions • IF: – Page fault on instr. fetch fault on instr. fetch – Misaligned memory access – Memory protection violation • ID: Undefined/illegal opcode • EX: Arithmetic exception • MEM: – Page fault on data fetch – Misaligned memory access – Memory protection violation • WB: None S. Ziavras MIPS Exceptions (2) Multiple exceptions may occur in same cycle because multiple instrs. execute concurrently E.g., LD IF ID EX MEM WB DADD IF ID EX MEM...
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This document was uploaded on 02/09/2014.

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