Appendix-C-m2-ziavras

Changes and new slides included reg reg reg reg dmem

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Unformatted text preview: Changes and new slides included MEM/WR mux EX/MEM M ALU U m mux ID/EX / Registers e Immediate Data Memory S. Ziavras Data Hazard Even with Forwarding DMem Ifetch Reg DMem Reg Ifetch Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included Ifetch Reg Reg Reg DMem ALU O r6 r and r6,r1,r7 d e or r8,r1,r9 r8 r Reg ALU Ifetch ALU I n lw r1, 0(r2) r1 s t r. sub r4,r1,r6 r4 ALU Time Time (clock cycles) Reg DMem Reg S. Ziavras Resolving This Load Hazard Resolving This Load Hazard • Adding hardware? ... not • Runtime detection? – Solution 1: stall • Compilation techniques? – Solution 2: rearrange the code Solution rearrange the code • What is the cost of load delays? 1 cycle for MIPS is the cost of load delays? cycle for MIPS Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Resolving the Load Data Hazard Resolving the Load Data Hazard Time (clock cycles) DMem Ifetch Reg Bubble Ifetch Bubble Reg Bubble Ifetch or r8,r1,r9 Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included Reg DMem Reg Reg DMem ALU and r6,r1,r7 Reg ALU sub r4,r1,r6 Ifetch ALU O r d e r lw r1, 0(r2) ALU I n s t r. Solution 1: stall Reg DMem S. Ziavras Software Scheduling to Avoid Load Hazards Try producing fast code for a = b + c; d = e – f; a, b, c, d ,e & f: stored in memory. Slow code Slow code: Fast code: code LW Rb,b LW LW Rc,c LW LW ADD Ra,Rb,Rc LW SW a,Ra ADD LW Re,e LW LW Rf,f SW SUB Rd,Re,Rf Rd SUB SW d,Rd SW Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included Solution 2 Rb,b Rc,c Rc,c Re,e Ra,Rb,Rc Rf,f a,Ra Rd,Re,Rf d,Rd S. Ziavras Instruction Set Connection • What is exposed about this organizational hazard in the instruction set? • k cycle delay? – bad, CPI is not part of ISA • k instruction slot delay – load should not be followed by use of the value in the next instructions value in the next k instructions • Nothing, but code can reduce run-time delays • MIPS did the transformation in the assembler Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Historical Perspective: Microprogramming Main Main Memory ADD SUB AND . . . DATA execution unit CPU control memory User p...
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