Appendix-C-m2-ziavras

Changes and new slides included s ziavras example one

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Unformatted text preview: l Hazard Hazard D.M.: Data Memory Time (clock cycles) Ifetch Reg Ifetch 5 DMem 6 Reg DMem Reg DMem Reg ALU O r d e r Instr 2 Reg 4 D.M. ALU Ifetch 3 ALU I n Load s t Instr 1 r. 2 ALU 1 Instr 3 7 Reg Reg DMem Reg Ifetch Instr 4 Structural Hazard Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Resolving Structural Hazards Resolving Structural Hazards • Definition of such hazard: attempt to use same hardware for two different acions at the same time • Solution 1: Wait Wait ⇒ must detect the hazard ⇒ must have mechanism to stall • Solution 2: Throw more hardware at the problem Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Detecting and Resolving Structural Hazard Time (clock cycles) Stall Ifetch Reg Ifetch 5 6 7 Reg DMem Reg Bubble Reg DMem Bubble Bubble Instr 3 Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included Ifetch Reg Reg Bubble ALU O r d e r Instr 2 Reg 4 D.M. ALU Ifetch 3 ALU I n Load s t Instr 1 r. 2 ALU 1 Bubble DMem Reg S. Ziavras Eliminating Structural Hazards at Design Time Next SEQ PC Next SEQ PC Adder Zero? RS1 RD RD RD MUX Sign Extend MEM/WB D Data Cache EX/MEM E ALU U MUX MUX M ID/EX X Imm Reg File IF/ID Instr r Cache e Address s Datapath RS2 WB Data 4 MUX Next PC Control Path Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Role of Instruction Set Design in St Structural Hazard Resolution • Simple to determine the sequence of resources used by an instruction – opcode tells it all tells it all • Uniformity in resource usage • MIPS approach => all instructions flow approach all instructions flow through same 5-stage pipeline Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Data Hazards Time (clock cycles) and r6,r1,r7 or Ifetch DMem Reg DMem Ifetch Reg DMem Ifetch Reg DMem Ifetch Reg ALU sub r4,r1,r3 Reg ALU Ifetch ALU O r d e r add r1,r2,r3 WB ALU I n s t r. MEM ALU IF ID/RF EX r8,r1,r9 xor r10,r1,r11 r10 Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included Reg Reg Reg Reg DMem S. Ziavras Reg Three Generic Data H...
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