Appendix-C-m2-ziavras

Culler copyright 2001 ucb changes and new slides

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: rogram plus data plus data order can change one of these is of these is mapped into one of these Fixed sequence of microinstructions for each macroinstruction Supported complex instr: sequence of simple micro-instrs (RTs). Pipelined micro-instr. processing, but very limited view. micro processing but very limited view Could not reorganize macroinstructions to enable pipelining Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Control Hazard on Branches => Three Stage Stall Reg DMem Ifetch Reg DMem Ifetch Reg DMem Ifetch Reg ALU r6,r1,r7 Ifetch DMem ALU 18: or Reg ALU 14: and r2,r3,r5 Ifetch ALU 10: beq r1,r3,36 ALU • Assume: the decision is made after a subtraction in the ALU • Not true for MIPS 22: add r8,r1,r9 36: xor r10,r1,r11 xor r10 Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included Reg Reg Reg Reg DMem S. Ziavras Reg Example: Branch Stall Impact Example: Branch Stall Impact • • If 30% branch, stall 3 cycles significant 2-part solution: 1. Determine branch taken or not sooner & 2. Compute taken branch address earlier • MIPS branch always tests if register = 0 or ≠ 0 branch always tests if register or • MIPS Solution: – Move Zero test to ID/RF stage Zero test to ID/RF stage – Adder to calculate new PC in ID/RF stage – 1 CLOCK CYCLE PENALTY FOR BRANCH VERSUS 3 Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Pipelined MIPS Datapath Adder Adder 4 RS1 RD RD RD MUX Sign Extend MEM/WB D Data Memory e EX/MEM E ALU U M MUX ID/EX Imm Reg File IF/ID Memory r Address s RS2 Zero? WB Data SEQ PC Memory Write Access Back MUX Instruction Instr. Decode Execute Fetch Reg. Fetch Addr. Calc Calc Next Next Next PC Data stationary control: local decode for each instr. phase / pipeline stage S. Ziavras Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included 4 Branch Hazard Alternatives #1: Stall until branch direction is clear #2: Predict Branch Not Taken – Execute successo...
View Full Document

This document was uploaded on 02/09/2014.

Ask a homework question - tutors are online