Appendix-C-m2-ziavras

Issued per clock cycle superscalar adapted from d

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Unformatted text preview: Ideal CPI + Aver. Stall cycles per Instr pipel. Cycle Time Ideal CPI × Pipel. depth unpipel. Speedup = × Ideal CPI + Pipel. stall CPI Cycle Time pipel. For simple RISC pipeline, CPI = 1: Cy Ti C cle Time Pipel. depth unpipel. × Speedup = Cycle Time 1 + Pipel. stall CPI pipel. Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Example: Evaluating Branch Alternatives Pipeline speedup = Pipeline depth 1 +Branch frequency× Branch penalty Assume: Conditional & Unconditional = 14%, 65% change PC Scheduling Branch scheme penalty Stall pipeline 3 Predict taken 1 Predict not taken 1 Delayed branch branch 0.5 CPI 1.42 1.05 1.09 1.07 Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included speedup v. stall 1.00 1.35 1.30 1.33 S. Ziavras Summary: Pipelining & Performance • Just overlap tasks; easy if tasks are independent • Speed Up ≤ Pipeline Depth; if ideal CPI is 1, then: Up Depth; if ideal CPI is then: Cycle Timeunpipel. Pipel. depth depth Speedup = × 1 + Pipel. stall CPI Cycle Timepipel. • Hazards limit performance on computers: – Structural: need more HW resources need more HW resources – Data (RAW,WAR,WAW): need forwarding, compiler scheduling – Control: delayed branch, prediction Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Summary (2) • Time is measure of performance: latency or throughput • CPI Law: CPU time = Seconds Program = Instrs Program Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included x Cycles Instr x Seconds Cycle S. Ziavras Relationship of Caches and Pipeline Memory D-$ I-$ WB Data M MUX Data Memory Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included RD EX/MEM RD ALU U MUX ID/EX Sign Imm Extend MEM/WB Zero? Reg File F RS1 RS2 MUX U Adder IF/ID Memory o Address e 4 Next SEQ SEQ PC A Adder Next PC RD S. Ziavras...
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