Appendix-C-m2-ziavras

Phase pipeline stage s ziavras adapted from d culler

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Unformatted text preview: r instructions in sequence – “Squash” instructions in pipeline if branch actually taken taken – Advantage of late pipeline state update – 47% of MIPS branches not taken on average – PC+4 already calculated, so use it to get next instruction Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras 4 Branch Hazard Alternatives (2) #3: Predict Branch Taken – 53% MIPS branches taken on average – But haven’t calculated branch target address in MIPS » MIPS still incurs 1 cycle branch still incurs cycle branch penalty » Some other machines: branch target known before outcome Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras 4 Branch Hazard Alternatives (3) #4: Delayed Branch – Define branch to take place AFTER a following instruction branch instruction instruction sequential successor1 sequential successor2 Branch delay ........ of length of length n sequential successorn ........ branch target if taken – 1 slot delay allows proper decision and branch target address in stage pipeline target address in 5 stage pipeline – MIPS uses this Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Delayed Branch • Where to get instrs. to fill branch delay slot? fill – Before branch instr. – From target address: only valuable when branch target address: only valuable when branch taken – From fall through: only valuable when branch not taken – Canceling branches allow more slots to be filled • Compiler effectiveness for single branch delay slot: effectiveness for single branch delay slot: – Fills about 60% of branch delay slots – About 80% of instrs. executed in branch delay slots useful in computation – About 50% (60% x 80%) of slots usefully filled • Delayed Branch downside: 7-8 stage pipelines, multiple instrs. issued per clock cycle (superscalar) Adapted from D. Culler. Copyright 2001 UCB. Changes and new slides included S. Ziavras Recall:Speed Up Equation for Pipelining CPI =...
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