Ziavras reduces reduces potential data hazard stalls

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Unformatted text preview: renaming Dynamic branch prediction Issuing multiple instrs. per cycle S. Ziavras Reduces Reduces Potential data hazard stalls (Appendix A) Control hazard stalls Data hazard stalls from true dependences Data hazard stalls & stalls hazard stalls stalls from antidependences & output dependences Control stalls Ideal CPI Technique HW speculation Dynamic memory disambiguation Loop unrolling Basic compiler pipeline scheduling scheduling Compiler dependence analysis, SW pipelining, trace scheduling HW support for compiler speculation Reduces Data hazard & control hazard stalls Data hazard stalls with memory Control hazard stalls Data hazard stalls (some in Appendix Appendix A) Ideal CPI, data hazard stalls (Appendix G) Ideal CPI, data hazard stalls, branch hazard stalls S. Ziavras Loop-Level Parallelism • • Exploit parallelism among iterations of a loop: simplest & most common way to increase amount of parallelism available among instrs parallelism available among instrs. Techniques – Loop...
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This document was uploaded on 02/09/2014.

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