chapter1-AppendixA-m2-ziavras

Alu cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6

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Unformatted text preview: ock cycles) DMem Reg DMem Reg ALU Ifetch DMem Reg Reg ALU O r d e r Ifetch ALU I n s t r. ALU Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Ifetch Some material is adapted from D. Culler & D. Patterson (UCB) Ifetch Reg Reg Reg DMem Reg S. Ziavras Limits Limits to pipelining • Hazards prevent next instruction from executing during during its designated clock cycle Some material is adapted from D. Culler & D. Patterson (UCB) Reg DMem Ifetch Reg DMem Ifetch Reg ALU DMem Ifetch Reg ALU O r d e r Ifetch ALU I n s t r. ALU – Structural hazards: attempt to use the same hardware to do two different things at once – Data hazards: Instruction depends on result of prior instruction still in the pipeline – Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches (branches and jumps). Time (clock cycles) Reg Reg Reg DMem Reg S. Ziavras 2) The Principle of Locality • The Principle of Locality: – Program accesses a relatively small portion of the address space at any instant of time. • Two Different Types of Locality: – Temporal Locality (Locality in Ti...
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This document was uploaded on 02/09/2014.

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