chapter1-AppendixA-m2-ziavras

Culler d patterson ucb 1 1 fractionenhanced enhanced s

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ) + Fraction enhanced Speedupenhanced Best you could ever hope to do: Speedupmaximum = Some material is adapted from D. Culler & D. Patterson (UCB) 1 (1 - Fractionenhanced ) enhanced S. Ziavras Amdahl Amdahl’s Law example • New CPU 10X faster • I/O bound server, so 60% time waiting for I/O Speedup overall = 1 (1 − Fraction enhanced Fraction )+ Speedup enhanced enhanced 1 1 = = = 1 . 56 0 . 64 (1 − 0.4 ) + 0.4 10 • Apparently, its human nature to be attracted by 10X faster, vs. keeping in perspective it’s just ~1 ~1.6X faster Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras 5) Processor performance equation inst count CPU time = Seconds Program Program = Instructions x Program Inst Count X Cycles Compiler X X Cycle f (X) Inst. Set. Cycle time x Seconds Instruction CPI CPI X Organization Technology Some material is adapted from D. Culler & D. Patterson (UCB) X X X S. Ziavras What What’s a Clock Cycle? Latch or register combinational logic • Old days: several levels of gates • Today: determined by...
View Full Document

This document was uploaded on 02/09/2014.

Ask a homework question - tutors are online