chapter1-AppendixA-m2-ziavras

Culler d patterson ucb cisc s ziavras risc vs cisc

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Unformatted text preview: D. Patterson (UCB) for S. Ziavras RISC Vs. CISC (2) RISC Vs. CISC (2) RISC outperforms CISC if the program length does not increase significantly MIPS rate MIPS rate = I f c= T × 10 6 CPI × 10 6 T=Ic x CPI x (1/f) >f ⎫ f f ⎪ RISC CISC RISC CISC > ⎬⇒ CPI < CPI × 10 6 × 10 6 CPI ⎪ CPI RISC CISC ⎭ RISC CISC f ⇒ MIPS RISC > MIPS Some material is adapted from D. Culler & D. Patterson (UCB) CISC S. Ziavras RISC Vs. CISC (3) RISC Vs. CISC (3) • RISC code is about 40% longer than CISC code ICRISC =~ 1.4 ICCISC • RISC has reduced complexity 4* CPIRISC << CPICISC • Boundary between CISC and RISC architectures Boundary has become blurred in recent years – VAX 9000, Motorola 88100, Intel i586: have both both CISC and RISC features Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras Intel 80x86 Intel 80x86 • A CISC success primarily due to – commercial importance of binary compatibility with PC software – transistor density increases predicted by Moore’s Law • RISC architecture internally RISC – Hardware translates 80x86 CISC instructions...
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