chapter1-AppendixA-m2-ziavras

Culler d patterson ucb s ziavras amd bulldozer 102011

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: wed as short vector (super)computers » Intel MMX: 64 bits (8 8-bit, 4 16-bit or 2 32-bit elements) » PowerPC AltiVec: 128 bits (vectors twice that length) » Intel extension for 128-bit vectors: new set of instrs. extension for 128 vectors new set of instrs (SSE: Streaming SIMD Extension) • SIMD: Single-Instruction Multiple-Data • Other exec. modes: SISD (uniprocessor), MIMD (independ. processors), MISD (pipelining?, systolic array?) Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras AMD Bulldozer (10/2011) supports • Intel's Advanced Vector Extensions (AVX) Intel instruction set 256-bit floating point operations • SSE4.1, SSE4.2, AES: Advanced Encryption Standard, CLMUL: Carry-Less Multiplication (Intel 2008) ISA extension for block cipher encryption encryption in Galois/Counter Mode • future 128-bit AMD instruction sets (XOP, FMA4 and CVT16) with similar functionality to the AMD SSE5 instruction set • 2 128-bit FPUs can be combined to form a 256-bit...
View Full Document

Ask a homework question - tutors are online