chapter1-AppendixA-m2-ziavras

Culler d patterson ucb s ziavras mips basic

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Unformatted text preview: (EBX)+4(add with displ.) = 6 bytes • Length of 80x86 instrs.: 1-17 bytes Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras IBM CodePack With PowerPC • • • • • • • • • For embedded systems Instr. cache contains full 32-bit instrs. cache full 32 instrs. Compressed code in RAM, ROM & disks Hardware decompresses instrs. as they’re fetched from memory on instr. cache miss Huffman encoding/compression of program Every program has its own encoding which is stored in onprogram has its own encoding which is stored in on chip 2 KB compression table Because of misaligned word boundaries, branches are possible with hash table in RAM – Compressed uncompressed address (like TLB) 10% lower performance lower performance 35-40% reduction in code size Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras MIPS Basic Instruction Formats • 2 addressing modes (immediate: 16 bits; displacement: 16 & 26 bits) • 32-bit instrs. * 64-bit address * byte-addressable memory Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras MIPS also has 2 instruction formats for floating-point operations Some material is adapted from D. Culler & D. Patterson (UCB) S. Ziavras MIPS Floating-Point Operations • • MOV.S & MOV.D copy single- or double-precision, respectively, FP reg. to...
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